1. Field of the Invention
This invention relates generally to circuit storage elements, and more particularly to flip-flops with a dynamic input stage.
2. Description of Related Art
Dynamic flip-flops are widely used in state of the art microprocessors. One particularly advantageous flip-flop that has a dynamic input stage and an output stage is disclosed in commonly owned U.S. Pat. No. 5,825,224, entitled "Edge-Triggered Dual-Rail Dynamic Flip-Flop With Self-Shut-Off Mechanism," issued to Klass et al. on Oct. 20, 1998, which is incorporated herein by reference in its entirety.
While the flip-flop of U.S. Pat. No. 5,825,224 is a significant advance over prior art configurations, there are certain configurations of the flip-flop that may have a charge-sharing problem. In these configurations, the output signal on one of the output terminals of the dynamic input stages momentarily changes during the evaluation phase. The momentary change may result in a state change on an output terminal of the flip-flop, which in turn can lead to erroneous results.
To better understand the limitations of the prior art flip-flop consider FIG. 1A, which is a schematic of a flip-flop 100 according to U.S. Pat. No. 5,825,224. Flip-flop 100 includes a three-input Exclusive OR circuit and a three-input Exclusive NOR circuit that introduce a charge-sharing problem within flip-flop 100.
In FIG. 1, elements with the same reference numeral as the reference number in FIG. 7 of U.S. Pat. No. 5,825,224 (the '224 patent) are the same element. Therefore, the operation of flip-flop 100 will be apparent to those of skill in the art in view of the description in the '224 patent.
Precharge PMOS transistors 101 to 106 are used to precharge nodes within the Exclusive OR and Exclusive NOR circuit. Precharge PMOS transistors 101 to 106 assure that there is no potential difference across the transistors in the combinatorial logic circuits during the precharge phase. Consequently, in the transition to the evaluation phase there is no spike or false evaluation on the output node that does not change state.
Assume that input signals A, B and C are either all a logic zero, or any two of the signals are a logic one at the start of the evaluation phase. Traces for signals A, B and C are presented in FIG. 1B. For all these combinations of input signals, the signal on line OUTN1 remains at a logic one level, while the signal on line OUTN2 is pulled to a logic zero level as the clock signal on clock line CLK goes active. See FIG. 1B.
As explained in the '224 patent, two inverter delays after the signal on line OUTN2 goes inactive, NMOS transistor S1 is turned off. NMOS transistor S2 remains turned-on, while keeper NMOS transistor K1 is turned-off. Consequently, output line OUTN2 is coupled to the Exclusive NOR circuitry through NMOS transistor S2.
If an input signal to the Exclusive NOR circuity changes, e.g., signal A as illustrated in FIG. 1B, the output signal of the Exclusive NOR circuitry may change, which in turn momentarily changes the output signal on output line OUTN2 as illustrated in FIG. 1B. However, pull-down device 4 prevents the signal on output line OUTN2 from going to a logic high level. Therefore, the output signal on output line OUTN2 has at most a momentary glitch 152 that is generated in response to input signal A changing state after the start of the evaluation phase. Momentary glitch 152 may cause a corresponding dip on output terminal/Q.
Flip-flop 100 is used to drive dynamic logic, which typically responds only to a low-to-high transition on a clock edge. Since the downstream dynamic logic driven by the signal on terminal/Q responds to the low-to-high transition on terminal/Q, glitch 152 does not affect the state of the logic. However, in general, in digital logic, glitches are undesirable.
Glitch 152 on line OUTN2 may be of sufficient magnitude to pass through inverters INV2 and INV3, which in turn causes shut-off transistor S1 to momentarily conduct. This can result in a low-to-high transition on output terminal Q, which in turn may result in a false evaluation by dynamic logic driven by the signal on output terminal Q. While glitch 152 alone may not be sufficient to cause inverter INV3 to change state, wire coupling may effectively amplify the glitch so that inverter INV3 does change state. Consequently, the performance of flip-flop 100 is dependent upon layout conditions combined with input state changes during the evaluation phase.
Consequently, utilization of flip-flop 100 requires an analysis to determine whether layout factors coupled with changes in input signals can result in spurious signals on either of the flip-flops' two output lines during the evaluation phase. Therefore, a more robust dynamic flip-flop is needed that has performance that is unaffected by input signal changes and layout considerations.